Field of the Invention
The present invention relates to a semiconductor device including an LDMOSFET (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor).
Description of Related Art
Among semiconductor devices including an LDMOSFET, there is a configuration employing a thick film SOI (Silicon On Insulator) substrate as a base to increase withstand voltage of the LDMOSFET.
FIG. 6 is a schematic sectional view of a semiconductor device including an LDMOSFET of high withstand voltage.
A thick film SOI substrate 102 forming a base of the semiconductor device 101 has a structure where an SOI layer 105 made of Si (silicon) is laminated on a silicon substrate 103 via a BOX (buried oxide) layer 104 made of SiO2 (silicon dioxide).
An annular deep trench 106 is formed by digging in from a top surface of the SOI layer 105. A deepest portion of the deep trench 106 reaches the BOX layer 104. An interior of the deep trench 106 is completely filled with a polysilicon 108 via a silicon oxide film 107. A region surrounded by the deep trench 106 is thereby made an element forming region that is insulatingly separated (dielectrically separated) from its surroundings.
An LDMOSFET is formed in the element forming region. Specifically, in the element forming region, a P-type body region 109 is formed along a side surface of the deep trench 106 in the SOI layer 105. A region 110 besides the body region 109 in the element forming region is an N−-type (low concentration N-type) drift region. An N+-type (high concentration N-type) source region 111 and a P+-type (high concentration P-type) body contact region 112 are formed adjacent to each other on a top layer portion of the body region 109. An N+-type drain region 113 is formed in a top layer portion of the drift region 110.
On a top surface of the drift region 110, a LOCOS oxide film 114 is formed between the body region 109 and the drain region 113. On the top surface of the SOI layer 105, a gate oxide film 115 is formed between the source region 111 and the LOCOS oxide film 114. A gate electrode 116 is formed on the gate oxide film 115.
With this structure, a high positive voltage applied to the drain region 113 (drain voltage) can be apportioned between a depletion layer formed in the drift region 110 and the BOX layer 104 to increase the withstand voltage of the LDMOSFET.
To further increase the withstand voltage of the LDMOSFET, an impurity concentration of the drift region 110 can be further decreased. However, if the impurity concentration of the drift region 110 is decreased, the depletion layer extends greatly toward the drain region 113 (a width in a depth direction of the depletion layer increases) and a depletion layer capacitance decreases. Because the drain voltage apportioned to the BOX layer 104 consequently decreases, the SOI layer 105 (drift region 110) must be made large in layer thickness to maintain the withstand voltage. For example, in a case where the layer thickness of the BOX layer 104 is 1.5 μm and the N-type impurity concentration of the drift region 110 is 3.5×1014/cm3, the SOI layer 105 must be made no less than 40 μm in thickness to obtain a withstand voltage of 600V. When the layer thickness of the SOI layer 105 is large, it is difficult to form the deep trench 106 and the semiconductor device takes trouble and time to manufacture.
The layer thickness of the BOX layer 104 may be increased to increase the drain voltage apportioned to the BOX layer 104, suppress the spread of the depletion layer in the drift region 110, and thereby avoid increasing the layer thickness of the SOI layer 105. However, a thick film SOI substrate 102 having a BOX layer 104 with a layer thickness of no less than 4 μm cannot be manufactured by current arts. Thus, even when the layer thickness of the BOX layer 104 is set to 4 μm to obtain a withstand voltage of 600V when the N-type impurity concentration of the drift region 110 is 3.5×1014/cm3, the SOI layer 105 cannot be made 40 μm or less in layer thickness.